Efficient storage of error correcting code information

A controller, comprising:

• a plurality of memory channel interfaces that each include a respective plurality of memory access interfaces, the plurality of memory access interfaces to operate independently of the other of the plurality of memory access interfaces;
• the plurality of memory channel interfaces including at least a first group of memory access interfaces to access a first data word group and a second group of memory access interfaces to access a second data word group;
• the plurality of memory channel interfaces including at least a first error correction memory access interface and a second error correction memory access interface, the first error correction memory access interface and the second error correction memory access interface to access a same memory component, the first error correction memory access interface to access a first group of check bits associated with the first data word group, the second error correction memory access interface to access a second group of check bits associated with the second data word group.