Apparatuses, methods, and systems for instructions to request a history reset of a processor core

A method comprising:

• generating a plurality of software thread runtime property histories with a hardware guide scheduler of a hardware processor;
• decoding a single instruction into a decoded single instruction with a decoder of the hardware processor, the single instruction having a field that identifies a control register;
• and
• executing the decoded single instruction with an execution circuit of the hardware processor to:
• check that an enable bit of the control register is set, and
• when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

• decoding a single instruction into a decoded single instruction with a decoder of a hardware processor, the single instruction having a field that identifies a control register;
• and
• executing the decoded single instruction with an execution circuit of the hardware processor to:
• check that an enable bit of the control register is set, and
• when the enable bit is set, to reset a plurality of software thread runtime property histories of a hardware guide scheduler of the hardware processor.