Overlapped-immediate/register-field-specifying instruction

A data processing method for an apparatus comprising processing circuitry to perform data processing, an instruction decoder to decode instructions to generate control signals to control the processing circuitry to perform the data processing, and a plurality of registers;

• the method comprising:
• the instruction decoder decoding an overlapped-immediate/register-field-specifying (OIRFS) instruction comprising an opcode field specifying an OIRFS-indicating opcode value, and an overlapped immediate/register field specifying an immediate value and a register specifier;
• and
• in response to the OIRFS instruction, the instruction decoder controlling the processing circuitry to use a selected register of the plurality of registers corresponding to the register specifier as a source register or destination register when performing a processing operation depending on the immediate value;
• in which:
• said overlapped immediate/register field includes at least one shared bit for which:
• for at least one encoding of the OIRFS instruction having the opcode field specifying said OIRFS-indicating opcode value, the instruction decoder decodes said at least one shared bit as part of the immediate value;
• and
• for at least one encoding of the OIRFS instruction having the opcode field specifying said OIRFS-indicating opcode value, the instruction decoder decodes said at least one shared bit as part of the register specifier.

A non-transitory storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of instructions of target program code;

• the computer program comprising:
• processing program logic to perform data processing;
• and
• instruction decoding program logic to decode instructions of the target program code to control the processing program logic to perform the data processing with reference to a register providing data structure representing a plurality of registers;
• in which:
• in response to an overlapped-immediate/register-field-specifying (OIRFS) instruction comprising an opcode field specifying an OIRFS-indicating opcode value, and an overlapped immediate/register field specifying an immediate value and a register specifier, the instruction decoding program logic is configured to control the processing program logic to perform a processing operation depending on an immediate value, using a selected register of the plurality of registers corresponding to the register specifier as a source register or destination register;
• and
• said overlapped immediate/register field includes at least one shared bit for which:
• for at least one encoding of the OIRFS instruction having the opcode field specifying said OIRFS-indicating opcode value, the instruction decoding program logic is configured to decode said at least one shared bit as part of the immediate value;
• and
• for at least one encoding of the OIRFS instruction having the opcode field specifying said OIRFS-indicating opcode value, the instruction decoding program logic is configured to decode said at least one shared bit as part of the register specifier.