US 2021/0240447 A1Published application

Fast digital multiply-accumulate (mac) by fast digital multiplication circuit

AssigneeQUALCOMM Incorporated

InventorsXia LI, Zhongze WANG, Periannan CHIDAMBARAM

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Abstract

Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.

Claims20

Dependent claims

A circuit for digital signal processing, comprising:

a first multiplier circuit configured to multiply a first portion of a first digital input signal with a first portion of a second digital input signal to generate a first multiplication signal;
a second multiplier circuit configured to multiply a second portion of the first digital input signal with a second portion of the second digital input signal to generate a second multiplication signal;
a first adder circuit configured to add the first portion and the second portion of the first digital input signal to generate a first addition signal;
a second adder circuit configured to add the first portion and the second portion of the second digital input signal to generate a second addition signal;
a third multiplier circuit configured to multiply the first addition signal and the second addition signal to generate a third multiplication signal;
a third adder circuit configured to add the first multiplication signal and the second multiplication signal to generate a third addition signal;
a subtraction circuit configured to subtract the third addition signal from the third multiplication signal to generate a subtraction signal;
and
one or more adder circuits configured to add a left-shifted version of the first multiplication signal, the second multiplication signal, and a left-shifted version of the subtraction signal.

6 more elements

A method for digital signal processing, comprising:

multiplying, via a first multiplier circuit, a first portion of a first digital input signal with a first portion of a second digital input signal to generate a first multiplication signal;
multiplying, via a second multiplier circuit, a second portion of the first digital input signal with a second portion of the second digital input signal to generate a second multiplication signal;
adding, via a first adder circuit, the first portion and the second portion of the first digital input signal to generate a first addition signal;
adding, via a second adder circuit, the first portion and the second portion of the second digital input signal to generate a second addition signal;
multiplying, via a third multiplier circuit, the first addition signal and the second addition signal to generate a third multiplication signal;
adding, via a third adder circuit, the first multiplication signal and the second multiplication signal to generate a third addition signal;
subtracting, via a subtraction circuit, the third addition signal from the third multiplication signal to generate a subtraction signal;
and
adding, via one or more adder circuits, a left-shifted version of the first multiplication signal, the second multiplication signal, and a left-shifted version of the subtraction signal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/778,749Filed 31 Jan 2020
Published: 5 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 7/5334
Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even: by using multiple bit scanning, i.e. by…
G06F 7/5443
For evaluating functions by calculation: sum of products
G06F 7/523
Multiplying; Dividing: multiplying only
G06F 7/5324
In parallel-parallel fashion, i.e. both operands being entered in parallel: partitioned, i.e. using repetitively a smaller parallel parallel…

Family

US 11,474,786 B2Related patent
US 2021/0240447 A1This patent

From the US filing history. Foreign family members aren’t listed.

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