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US 2021/0240442 A1Published application
Low-power compute-in-memory bitcell
AssigneeQUALCOMM Incorporated
InventorsAnkit SRIVASTAVA, Seyed Arash MIRHAJ, Guoqing MIAO, Seyfi BAZARJANI
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Abstract
A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.
Claims35
A compute-in-memory storage cell, comprising:
- a pair of cross-coupled inverters having a first output node for a stored bit;
- a read bit line;
- a word line having a voltage responsive to an input bit;
- a capacitor having a first plate connected to the read bit line;
- and
- a first pass transistor connected between the first output node and a second plate of the capacitor and having a gate connected to the word line.
3 more elements
A compute-in-memory storage cell, comprising:
- a pair of cross-coupled inverters having a first output node for a stored bit;
- a read bit line;
- a capacitor having a first plate connected to the read bit line;
- and
- a first transmission gate connected between the first output node and a second plate of the capacitor, wherein the first transmission gate is configured to close in response to an input bit being true and is configured to open in response to the input bit being false.
2 more elements
A multiply-and-accumulate circuit, comprising:
- a plurality of compute-in-memory storage cells arranged into a plurality of columns, wherein each column includes a read bit line, and wherein each compute-in-memory storage cell in each column includes a logic gate configured to multiply an input bit with a stored bit and includes a capacitor having a first plate connected to the column's read bit line and having a second plate connected to an output node for the logic gate.
A compute-in-memory method, comprising:
- during a reset phase, charging a read bit line for a column of compute-in-memory storage cells to a power supply voltage while a first plate for a capacitor in each compute-in-memory storage cell is connected to the read bit line and while a second plate for each capacitor in each compute-in-memory storage cell is grounded;
- during a calculation phase following the reset phase in each compute-in-memory storage cell, multiplying a corresponding bit of an input vector with a stored bit for the compute-in-memory storage cell to drive the second plate of the compute-in-memory storage cell's capacitor with a multiplication signal while the read bit line remains charged to the power supply voltage;
- and
- during an accumulation phase following the calculation phase, isolating the read bit line from a power supply node for the power supply voltage while the second plate of each compute-in-memory storage cell's capacitor is grounded to develop an accumulation voltage on the read bit line.
1 more element
Dependencies are inferred from the claim text.