Computation in-memory using 6-transistor bit cells

A device, comprising:

• a bit cell configured to store a filter weight;
• and
• a multiply and average (MAV) circuit coupled to the bit cell, the MAV circuit having an analog voltage input and configured to:
• charge a first capacitor and a second capacitor to the analog voltage;
• and
• discharge one of the first capacitor and the second capacitor responsive to the filter weight.

A method, comprising:

• storing a filter weight in a bit cell;
• receiving, by a multiply and average (MAV) circuit, an analog voltage;
• charging, by the MAV circuit, a first capacitor and a second capacitor to the analog voltage;
• and
• discharging, by the MAV circuit, one of the first capacitor and the second capacitor responsive to the filter weight.

A device, comprising:

• a first bit cell having a first terminal and a second terminal;
• a first bit line coupled to the first terminal;
• a second bit line coupled to the second terminal;
• a second bit cell having a third terminal and a fourth terminal;
• a third bit line coupled to the third terminal;
• a fourth bit line coupled to the fourth terminal;
• and
• a multiply and average (MAV) circuit coupled to the first, second, third, and fourth bit lines, the MAV circuit including:
• a first capacitor;
• a second capacitor;
• a first transistor coupled to the first capacitor and to a ground terminal, the first transistor having a first transistor control terminal coupled to the first bit line;
• a second transistor coupled to the second capacitor and to the ground terminal, the second transistor having a second transistor control terminal coupled to the second bit line;
• a third transistor coupled to the first capacitor and to the ground terminal, the third transistor having a third transistor control terminal coupled to the third bit line;
• and
• a fourth transistor coupled to the second capacitor and to the ground terminal, the fourth transistor having a fourth transistor control terminal coupled to the fourth bit line.

A device, comprising:

• a bit cell having a first terminal and a second terminal;
• a first bit line coupled to the first terminal;
• a second bit line coupled to the second terminal;
• and
• a multiply and average (MAV) circuit coupled to the first bit line and the second bit line, the MAV circuit including:
• a first capacitor;
• a second capacitor;
• and
• a switching network configured to:
• responsive to the second bit line being logic low, couple the first capacitor to a negative voltage interconnect and couple the second capacitor to a positive voltage interconnect;
• and
• responsive to the first bit line being logic low, couple the first capacitor to the positive voltage interconnect and couple the second capacitor to the negative voltage interconnect.