US 2021/0240382 A1Published application

Device and method for checking register data

AssigneeRealtek Semiconductor Corp.

InventorsZAN LI, PAN-TING JIANG

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Abstract

Disclosed is a register data checking device including: an original parity-bit generator generating an original parity bit according to register data to be inputted into a register, and then writing the original parity bit to the register; and a detecting circuit. The detecting circuit includes: a scanning circuit reading the register data and the original parity-bit from the register; an arbitrator enabling the scanning circuit when an access status of the register is free, and thereby forwarding the register data and the original parity bit from the scanning circuit; at least one controlled parity-bit generator generating a controlled parity bit according to the register data from the arbitrator when the access status of the register is free; and at least one parity-bit checking circuit comparing the original parity bit from the arbitrator with the controlled parity bit when the access status is free, and thereby outputting a check result.

Claims14

Dependent claims

A register data checking device, comprising:

an original parity-bit generator configured to generate an original parity bit according to register data to be inputted into a register, and then writing the original parity bit to the register;
and
a detecting circuit including a scanning circuit, an arbitrator, at least one controlled parity-bit generator, and at least one parity-bit checking circuit, wherein:
the scanning circuit is configured to read the register data and the original parity-bit from the register according to a register address;
the arbitrator is configured to disable the scanning circuit on condition that a status signal is indicative of an access status of the register being busy;
the arbitrator is configured to enable the scanning circuit on condition that the status signal is indicative of the access status of the register being free, and thereby forward the register data and the original parity-bit from the scanning circuit to the at least one controlled parity-bit generator and at least one parity-bit checking circuit respectively;
the at least one controlled parity-bit generator is configured to generate a controlled parity bit according to the register data from the arbitrator on condition that the status signal is indicative of the access status of the register being free;
and
the at least one parity-bit checking circuit is configured to compare the original parity bit from the arbitrator with the controlled parity bit on condition that the status signal is indicative of the access status of the register being free, and thereby output a check result indicating whether the register data come from the register are erroneous.

6 more elements

A register data checking method, comprising:

generating an original parity bit according to register data to be inputted into a register, and then writing the original parity bit to the register;
generating a next original parity bit according to next register data to be inputted into a next register, and then writing the next original parity bit to the next register;
reading the register data and the original parity-bit from the register according to a register address;
generating a controlled parity bit according to the register data come from the register;
comparing the controlled parity bit with the original parity bit, and thereby outputting a check result indicating whether the register data come from the register are erroneous;
updating the register address and thereby obtaining a next register address;
reading the next register data and the next original parity bit from the next register according to the next register address;
generating a next controlled parity bit according to the next register data come from the next register;
and
comparing the next controlled parity bit with the next original parity bit, and thereby outputting a next check result indicating whether the next register data come from the next register are erroneous.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/139,376Filed 31 Dec 2020
Priority: CN 202010079091.83 Feb 2020
Published: 5 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
G06F 21/64
Protecting data: protecting data integrity, e.g. using checksums, certificates or signatures
G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/0673
In-line storage system: single storage device

Family

US 11,630,600 B2Related patent
US 2021/0240382 A1This patent

From the US filing history. Foreign family members aren’t listed.

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