US 2021/0240380 A1 · METHOD AND APPARATUS FOR PERFORMING AN ERASE OPERATION COMPRISING A SEQUENCE OF MICRO-PULSES IN A MEMORY DEVICE

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

Claims20

Dependent claims

A memory device, comprising:

a host interface, to receive an erase command from a memory controller coupled with the memory device, to erase at least a portion of data stored in the memory device, wherein the erase command comprises a sequence of erase segments that provide an erase voltage to the memory device, wherein the memory controller is to generate the erase command in response to a request provided by a host coupled with the memory controller, wherein the host is to initiate memory access requests to be executed by the memory device;
and
a control circuit coupled with the host interface, to control an execution of the erase command in a memory cell array of the memory device, to erase the portion of data.

Dependencies are inferred from the claim text.

Facts

Application

16/777,812Filed 30 Jan 2020

Published

5 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 3/0652
Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems: erasing, e.g. deleting, data cleaning, moving…
G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups
G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/0611
Improving I/O performance: in relation to response time

Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory device

Life of this patent

Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory device

Life of this patent

Abstract

Claims20