Display device
AssigneeSamsung Display Co., Ltd.
InventorsGwon-Heon RYU, Yang Gyu JANG, Kook Hyun CHOI, Beom Jun KIM, Hyung Gi JUNG
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a display device including a substrate, a gate line on the substrate, a data line crossing the gate line, a pixel connected to the gate line and the data line, and a dummy data line disposed at an edge on the substrate and crossing the gate line, wherein the dummy data line includes openings that is disposed on a portion that is near an overlapping portion with the gate line, and portions of the dummy data line separated by the openings are electrically insulated from each other.
Claims20
A display device comprising:
- a substrate;
- a gate line on the substrate;
- a data line crossing the gate line;
- a pixel connected to the gate line and the data line;
- and
- a dummy data line disposed on an edge of the substrate and crossing the gate line,
- wherein the dummy data line includes openings that are disposed on a portion that is near an overlapping portion with the gate line, and
- portions of the dummy data line separated by the openings are electrically insulated from each other.
A display device comprising:
- a substrate;
- a gate line on the substrate;
- a data line and a reference voltage line crossing the gate line;
- a pixel connected to the gate line, the data line, and the reference voltage line;
- and
- a dummy reference voltage line disposed on an edge of the substrate, and crossing the gate line,
- wherein the dummy reference voltage line includes openings disposed on a portion that is near the overlapping portion with the gate line, and
- portions of the dummy reference voltage line separated by the openings are electrically insulated from each other.
A display device comprising:
- a substrate;
- a gate line and a data line disposed on the substrate and crossing each other;
- a reference voltage line disposed on the substrate and receiving a predetermined voltage;
- a first transistor and a second transistor connected to the gate line and the data line;
- a third transistor connected to the gate line, the second transistor, and the reference voltage line;
- a first sub-pixel electrode connected to the first transistor;
- a second sub-pixel electrode connected to the second transistor;
- and
- a dummy data line disposed on an edge of the substrate and crossing the gate line,
- wherein the dummy data line includes openings disposed on a portion that is near an overlapping portion with the gate line, and
- portions of the dummy data line separated by the openings are electrically insulated from each other.
Dependencies are inferred from the claim text.