In-storage logic for hardware accelerators

A method, comprising:

• identifying a logic operation to be performed using a memory cell transistor;
• generating a word line voltage based on the logic operation;
• setting a threshold voltage of the memory cell transistor based on the logic operation;
• determining a first current threshold and a second current threshold greater than the first current threshold based on the logic operation;
• setting a gate of the memory cell transistor to the word line voltage;
• sensing a memory cell current flowing through the memory cell transistor while the gate of the memory cell transistor is set to the word line voltage, the sensing the memory cell current is performed subsequent to setting the threshold voltage of the memory cell transistor;
• generating a logical result based on a comparison of the memory cell current flowing through the memory cell transistor with both the first current threshold and the second current threshold;
• and
• storing the logical result.

An apparatus, comprising:

• a NAND string including a memory cell transistor;
• one or more control circuits;
• and
• a programmable sense amplifier in communication with the NAND string and the one or more control circuits, the one or more control circuits configured to acquire a first operand and a second operand associated with a logic operation, the one or more control circuits configured to set a threshold voltage of the memory cell transistor based on the first operand and bias a gate of the memory cell transistor to a gate voltage based on the second operand, the programmable sense amplifier configured to acquire a first current threshold and a second current threshold based on the logic operation, the programmable sense amplifier configured to generate a data value for the logic operation via comparison of the first current threshold and the second current threshold with a memory cell current of the memory cell transistor while the gate of the memory cell transistor is biased to the gate voltage.