System and method for compensating for sdram signal timing drift through periodic write training

An apparatus for compensating for signal timing drift in a synchronous dynamic random access memory (SDRAM) system, comprising:

• a host coupled to an SDRAM via a link, the host comprising a processor system, the host configured to:
• control write signal timing training performed a plurality of times at periodic intervals interspersed with mission-mode SDRAM traffic, the write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read, the write signal timing training performed a plurality of times producing a corresponding plurality of test result samples;
• analyze the plurality of test result samples independently of mission-mode SDRAM traffic;
• and
• adjust mission-mode timing of a plurality of SDRAM data bit signals relative to an SDRAM write clock signal based on an analysis of the plurality of test result samples.

An apparatus for compensating for signal timing drift in a synchronous dynamic random access memory (SDRAM) system, comprising:

• means for performing write signal timing training a plurality of times at periodic intervals interspersed with mission-mode SDRAM traffic, the write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read, the write signal timing training performed a plurality of times producing a corresponding plurality of test result samples;
• means for analyzing the plurality of test result samples independently of mission-mode SDRAM traffic;
• and
• means for adjusting mission-mode timing of a plurality of SDRAM data bit signals relative to an SDRAM write clock signal based on an analysis of the plurality of test result samples.

A method for compensating for signal timing drift in a synchronous dynamic random access memory (SDRAM) system, comprising:

• performing write signal timing training a plurality of times at periodic intervals interspersed with mission-mode SDRAM traffic, the write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read, the write signal timing training performed a plurality of times producing a corresponding plurality of test result samples;
• analyzing the plurality of test result samples independently of mission-mode SDRAM traffic;
• and
• adjusting mission-mode timing of a plurality of SDRAM data bit signals relative to an SDRAM write clock signal based on an analysis of the plurality of test result samples.