Sensing techniques for a memory cell

A method, comprising:

• coupling a memory cell with a sense component based at least in part on activating a first transistor using a first voltage;
• activating a second transistor after activating the first transistor, wherein the first voltage is modified to a second voltage based at least in part on activating the second transistor;
• coupling the sense component with the first transistor after activating a third transistor, wherein a third voltage associated with a first node coupled with the sense component is modified by the second voltage based at least in part on activating of the third transistor;
• and
• determining a logic state of the memory cell by comparing the third voltage with a reference voltage at a second node coupled with the sense component.

An apparatus, comprising:

• a memory cell;
• a first transistor configured to couple the memory cell with a sense component based at least in part on applying a first voltage to a node coupled with the first transistor, wherein the first transistor is configured to be activated to cause the first voltage to change to a second voltage;
• a second transistor configured to couple the first transistor with the sense component, wherein the second transistor is configured to be activated to apply the second voltage to a first node of the sense component;
• a third transistor configured to couple a reference voltage source with the sense component, wherein the third transistor is configured to be activated to apply a reference voltage associated with the reference voltage source to a second node of the sense component;
• and
• the sense component configured to determine a logic state of the memory cell by comparing the second voltage with the reference voltage.

An apparatus, comprising:

• a memory array;
• and
• a controller coupled with the memory array and configured to cause the apparatus to:
• couple a memory cell of the memory array with a sense component based at least in part on activating a first transistor using a first voltage;
• activate a second transistor after activating the first transistor, wherein the first voltage is modified to a second voltage based at least in part on activating the second transistor;
• couple the sense component with the first transistor after activating a third transistor, wherein a third voltage associated with a first node coupled with the sense component is modified by the second voltage based at least in part on activating of the third transistor;
• and
• determine a logic state of the memory cell by comparing the third voltage with a reference voltage at a second node coupled with the sense component.