Method of controlling on-die termination and system performing the same

A memory system operating in synchronization with an operation clock signal pair, the memory system comprising:

• a plurality of memory ranks, each memory rank including a plurality of memory devices, and each memory device including first and second mode registers for storing a target on-die termination (ODT) resistance value and a non-target on-die termination (ODT) resistance value respectively;
• a memory controller configured to set the first and second mode registers in each memory device and to perform a write operation on one of the plurality of memory ranks, the memory controller including a third mode register for storing a memory controller on-die termination (ODT) resistance value;
• a control bus shared by the plurality of memory ranks and coupled to the memory controller, and through the control bus, the memory controller transmitting a first CAS command and a write command to the plurality of memory ranks for a write operation;
• a data bus shared by the plurality of memory ranks and coupled to the memory controller, and through the data bus, the memory controller transmitting write data to the plurality of memory ranks;
• a plurality of rank selection signals, each of which connecting the memory controller to corresponding memory rank, wherein, when a first rank selection signal connected to a first memory rank among the plurality of memory ranks is enabled while the first memory rank receiving the first CAS command and the write command, the first memory rank operates as a write target memory rank and other memory ranks not selected by respective rank selection signals remain as write non-target memory ranks during the write operation;
• and
• a data strobe signal pair (WCK_t/WCK_c) shared by the plurality of memory ranks and coupled to the memory controller, wherein the write data are transmitted in synchronization with the data strobe signal during the write operation, and toggling frequency of the data strobe signal pair is higher than toggling frequency of the operation clock signal pair,
• wherein a first ODT circuit of the write target memory rank is configured to provide the target ODT resistance value on the data bus and second ODT circuits of the write non-target memory ranks are configured to provide the non-target ODT resistance value on the data bus during the write operation and a third ODT circuit of the memory controller is disabled during the write operation, and
• wherein the target ODT resistance value and the non-target ODT resistance value are different from each other.