On-chip training neuromorphic architecture

A neuromorphic architecture enabling on-chip training, comprising:

• one or more synapse arrays in which synapse devices having a preset conductance are arranged in a cross-bar shape;
• an input layer the supplies an input signal to a first synapse array;
• a final neuron layer that includes a forward neuron configured to perform a forward propagation operation of a neural network and a backward neuron configured to perform a backward propagation operation of the neural network and is connected to an output terminal of a last synapse array;
• one or two or more neuron layers that include a forward neuron configured to perform the forward propagation operation of the neural network, a backward neuron configured to perform the backward propagation operation of the neural network, and a memory that stores signals used during a weighted value update operation of the neural network and being arranged between the remaining synapse arrays except for the first synapse array and the last synapse array;
• and
• an error calculation circuit that is input with a target signal and an output signal of the forward neuron of the final neuron layer and detects and outputs an error value between the input target signal and the input output signal of the final neuron layer,
• wherein conductances of the synapse devices represent weighted values of the neural network and are changed by the weighted value update operation.