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US 2021/0232745 A1Published application
Method and system for semiconductor wafer defect review
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Pin CHOU, Chun-Wen WANG, Meng Ku CHI, Yan-Cheng CHEN, Jun-Xiu LIU
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Abstract
A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.
Claims20
A method, comprising:
- capturing a test image (208) of a semiconductor wafer (104);
- generating a simulated integrated circuit layout (404) by analyzing the test image;
- and
- identifying defects in the semiconductor wafer based on the simulated integrated circuit layout.
1 more element
A method, comprising:
- training, with a machine learning process, a simulated layout generation system (106) to generate simulated integrated circuit layouts;
- providing a test image (208) of a semiconductor wafer (104) to the simulated layout generation system;
- generating a simulated integrated circuit layout (404) with the simulated layout generation system;
- and
- comparing the simulated integrated circuit layout to a reference integrated circuit layout (408).
2 more elements
A system, comprising:
- a simulated layout generation system (106) configured to receive a test image of a semiconductor wafer (104) and to generate a simulated integrated circuit layout (404) based on the test image;
- and
- a defect detection system (108) configured to compare the simulated integrated circuit layout to a reference integrated circuit layout (402) and to detect a defect in the semiconductor wafer based on a difference between the simulated integrated circuit layout and the reference integrated circuit layout.
Dependencies are inferred from the claim text.