System and method for secure, fast communications between processors on complex chips

A system for secure and fast communication between processors on complex chips, comprising:

• a complex chip comprising at least two or more processors and a memory for each processor;
• store pre-trained reference codebook embedded as firmware in the memory of a first processor and in the memory of a second processor, wherein the pre-trained reference codebook is generated using training data to identify chunklets and their associated codewords, and store the codewords in the reference codebook;
• and
• store a deconstruction algorithm embedded as firmware in the memory of the first processor and in the memory of the second processor, wherein the deconstruction algorithm, when operating on the first processor, cause the first processor to:
• receive data;
• deconstruct the data into a plurality of chunklets;
• encode the data using the pre-trained reference codebook by:
• retrieve the codeword for each chunklet from the pre-trained reference codebook;
• and
• store a reconstruction algorithm embedded as firmware in the memory of the first processor and in the memory of the second processor, wherein the reconstruction algorithm, when operating on the second processor, cause the second processor to:
• receive a codeword;
• retrieve the chunklet for each received codeword from the pre-trained reference codebook;
• and
• assemble the chunklets to reconstruct the data.