Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (hls) code

A system, comprising:

• a memory storing instructions;
• one or more communication interfaces;
• one or more hardware processors coupled to the memory via the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to:
• obtain a machine programming language (MPL) code from a user, wherein the MPL code comprises at least one of one or more printf statements and one or more scanf statements for debugging the MPL code;
• and
• a synthesizable logic that converts the MPL code comprising the at least one of one or more printf statements and one or more scanf statements to register transfer language (RTL) instructions, wherein the RTL instructions comprises a logic,
• wherein the one or more hardware processors synthesize, at run-time, the at least one of one or more printf statements and one or more scanf statements by:
• executing, the logic, wherein the logic when executed interacts with a local field-programmable gate array (FPGA) memory and writes one or more debug messages on the local FPGA memory;
• transmitting the one or more written debug messages to a Direct Memory Access (DMA) block;
• transmitting the one or more written debug messages by the DMA block to a host memory based on an interaction of the DMA block with a controller;
• and
• writing, via a device driver executed by the one or more hardware processors, the one or more transmitted debug messages to a file system, wherein an output file is generated that comprises the one or more debug messages, and wherein a debug message reader comprised in the system reads the one or more debug messages and prints the one or more debug messages thereof at run time, and wherein the printed one or more debug messages are indicative of (i) an execution flow of the (RTL) instructions at run time, and (ii) one or more values associated with one or more parameters comprised in the (RTL) instructions.

One or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause synthesizing printf statements for generating debug messages in High-Level Synthesis (HLS) code by:

• obtaining, via the one or more hardware processors, a machine programming language (MPL) code from a user, wherein the MPL code comprises the at least one of one or more printf statements and one or more scanf statements for debugging the MPL code;
• converting, via a synthesizable logic, the MPL code comprising the at least one of one or more printf statements and one or more scanf statements to register transfer language (RTL) instructions, wherein the RTL instructions comprises a logic;
• and
• synthesizing, at run-time, the at least one of one or more printf statements and one or more scanf statements by:
• executing, via the one or more hardware processors, the logic, wherein the logic when executed interacts with a local field-programmable gate array (FPGA) memory and writes one or more debug messages on the local FPGA memory;
• transmitting, via the one or more hardware processors, the one or more written debug messages to a Direct Memory Access (DMA) block;
• transmitting, via the one or more hardware processors, the one or more written debug messages by the DMA block to a host memory based on an interaction of the DMA block with a controller;
• and
• writing, via a device driver executed by the one or more hardware processors, the one or more transmitted debug messages to a file system, wherein an output file is generated that comprises the one or more debug messages, wherein a debug message reader reads the one or more debug messages and prints the one or more debug messages thereof, and wherein the printed one or more debug messages are indicative of (i) an execution flow of the (RTL) instructions, and (ii) one or more values associated with one or more parameters comprised in the (RTL) instructions.