Dual path sequential element to reduce toggles in data path

A computing system comprising:

• a processor, having one or more processors;
• and
• memory, coupled to the processor, to store one or more instructions to be executed by the processor,
• the processor comprising switching logic circuitry to cause signals for a single data path of the processor to be directed to at least two separate data paths of the processor,
• wherein the at least two separate data paths of the processor comprise a first path and a second path, wherein the first path or the second path is to comprise one or more phase flops to control flop instantiation.