Method of making six transistor sram cell using connections between 3d transistor stacks

A three dimensional (3D) semiconductor device comprising:

• a first stack of first transistor structures formed on a substrate, each first transistor structure comprising a channel extending in a horizontal direction along a surface of the substrate and a pair of S/D regions formed on opposite ends of the channel, wherein the first transistor structures are stacked along a vertical direction along thickness direction of the substrate such that channel regions of the first stack are positioned over one another and S/D regions of the first stack are positioned over one another;
• a second stack of second transistor structures formed on the substrate adjacent to the first stack, each second transistor structure comprising a channel extending in the horizontal direction and a pair of S/D regions formed on opposite ends of the channel, wherein the second transistor structures are stacked along the vertical direction such that channel regions of the second stack are positioned over one another and S/D regions of the second stack are positioned over one another, the second stack being formed adjacent to the first stack such that stacked S/D regions at an end of the first stack are facing respective stacked S/D regions at an end of the second stack;
• a connecting structure that extends in the horizontal direction to physically connect a first pair of facing S/D regions to each other;
• and
• first and second metal interconnect structures connected to respective S/D regions in a second pair of facing S/D regions of the first and second stack, the second pair of facing S/D regions being physically separated from one another of the first and second stack as a separated pair of facing S/D regions which are physically separated from each other.

A method of fabricating a semiconductor device, the method comprising:

• forming a first stack of transistor channels adjacent to a second stack of transistor channels, the stacks of transistor channels being gate-all-around transistor channels that extend horizontally and that are aligned vertically in that transistor channels are positioned over each other;
• forming first source/drain regions on transistor channels of the first stack while transistor channels of the second stack are covered;
• forming source/drain regions on transistor channels of the second stack while source/drain regions on the first stack are covered, wherein forming source/drain regions on transistor channels of the second stack is executed with step-wise uncovering of channel ends to form either N-doped or P-doped source/drain regions selectively;
• growing first adjacent source/drain regions together between the first stack and the second stack while maintaining second adjacent source/drain regions physically separated from each other;
• and
• electrically connecting transistors in the first stack and the second stack to form an SRAM cell.