Chip package structure and manufacturing method thereof

A manufacturing method of a chip package structure, comprising:

• providing a carrier with an adhesive layer formed;
• providing at least one chip and at least one thermally conductive element, wherein the respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface, and the respective thermally conductive element is disposed on the back surface of the respective chip;
• bonding the at least one chip on the carrier, wherein the electrodes of the respective chip are directly in contact with the adhesive layer;
• forming a molding compound on the carrier to cover the adhesive layer and encapsulate the at least one chip and the at least one thermally conductive element;
• removing a portion of the molding compound such that the molding compound exposes a top surface of the respective thermally conductive element;
• removing the carrier and the adhesive layer to expose the electrodes of the respective chip and a lower surface of the molding compound, wherein a bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound;
• and
• forming a redistribution layer on the lower surface of the molding compound, wherein the redistribution layer is electrically connected to the electrodes of the respective chip.