Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate including a cell array region and a peripheral circuit region that surrounds the cell array region;
• a plurality of conductive lines disposed on the substrate in the peripheral circuit region;
• a plurality of conductive pads disposed on and spaced apart from the plurality of conductive lines, the plurality of conductive pads are spaced apart from each other;
• a plurality of dielectric patterns disposed between the plurality of conductive lines and the plurality of conductive pads, the plurality of dielectric patterns are spaced apart from each other;
• a plurality of bottom electrodes disposed on the plurality of conductive pads, each of the plurality of bottom electrodes are connected in common to one conductive pad of the plurality of conductive pads;
• a dielectric layer conformally covering the bottom electrodes;
• and
• a top electrode disposed on the dielectric layer and filling spaces between the plurality of bottom electrodes, between the plurality of conductive pads, and between the plurality of dielectric patterns.

A semiconductor device, comprising:

• a substrate including a cell array region and a peripheral circuit region that surrounds the cell array region, the peripheral circuit region including a first region and a second region that surrounds the first region;
• a plurality of word lines disposed in the cell array region, the plurality of word lines extending in a first direction that is parallel to an upper surface of the substrate;
• a plurality of bit lines that intersect the word lines and extend in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction;
• a plurality of first contacts disposed between the plurality of bit lines and the substrate;
• a plurality of second contacts disposed between adjacent bit lines, the plurality of second contacts contacting the substrate;
• a plurality of landing pads disposed on corresponding second contacts;
• a first conductive pad disposed on the substrate in the first region;
• a plurality of conductive lines disposed on the substrate in the second region, top surfaces of the conductive lines are located at a same level as a level of top surfaces of the landing pads and a top surface of the first conductive pad;
• a second conductive pad disposed on and spaced apart from the conductive lines;
• a dielectric pattern disposed between the conductive lines and the second conductive pad;
• a plurality of first bottom electrodes disposed on and connected to corresponding landing pads in the cell array region;
• a plurality of second bottom electrodes disposed on and connected in common to the first conductive pad in the first region;
• and
• a plurality of third bottom electrodes disposed on and connected in common to the second conductive pad in the second region,
• wherein a height of each of the plurality of first and second bottom electrodes is greater than a height of each of the plurality of third bottom electrodes, and
• wherein top surfaces of the first, second, and third bottom electrodes are located at a same level.