Testing device and testing method
AssigneeKabushiki Kaisha Tokai Rika Denki Seisakusho
InventorSunao NAGAI
Life of this patent
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AssigneeKabushiki Kaisha Tokai Rika Denki Seisakusho
InventorSunao NAGAI
Estimating the term…
When testing a reset circuit, a first register outputs a set signal to an OR circuit of the reset circuit so that a logic circuit is not reset even if an input voltage is low. Further, when testing the reset circuit, the first register turns off a regulator circuit by outputting a set signal from a second register to the regulator circuit and supplying the input voltage to the reset circuit from an external device via a voltage application terminal. Subsequently, the input voltage supplied from the voltage application terminal is varied and an output signal of a comparator output from a signal output circuit through an external terminal is checked to test whether the reset circuit is actuated normally.
A testing device, comprising:
A method for testing, comprising:
Dependencies are inferred from the claim text.