Decision feedback equalizer circuit and semiconductor integrated circuit that includes decision feedback equalizer circuit

A semiconductor integrated circuit comprising:

• a decision feedback equalizer circuit that equalizes a differential signal using a first equalizer circuit and a second equalizer circuit implemented in parallel;
• a demultiplexer that performs serial/parallel conversion for an output signal of the decision feedback equalizer circuit;
• and
• a clock regeneration circuit that regenerates a clock signal from the output signal of the decision feedback equalizer circuit, wherein
• each of the first equalizer circuit and the second equalizer circuit includes:
• an adder circuit;
• and
• a comparator configured to alternatingly perform refreshing and sampling for a differential signal output from the adder circuit in response to the clock signal, and
• the respective comparator includes:
• a differential amplifier circuit configured to output a differential signal having same values in a refresh period in which the refreshing is performed, and output a differential signal corresponding to the differential signal output from the adder circuit in a sampling period in which the sampling performed;
• and
• a latch circuit configured to perform a decision operation based on a comparison between a first signal and a second signal that form the differential signal output from the adder circuit in the sampling period, and to latch a decision result of the decision operation, and
• the adder circuit in the first equalizer circuit controls the differential signal input to the decision feedback equalizer circuit based on the decision result latched by the latch circuit in the second equalizer circuit, and
• the adder circuit in the second equalizer circuit controls the differential signal input to the decision feedback equalizer circuit based on the decision result latched by the latch circuit in the first equalizer circuit.