Method for demodulating digital signals using multiple digital demodulators

A method comprising:

• receiving a sequence of digital signal samples coming from at least one modulated analog signal, the sequence of digital signal samples comprising a first sample sub-sequence and a second sample sub-sequence different from the first sample sub-sequence,
• forming a first sample block comprising the first sample sub-sequence, wherein the first sample sub-sequence comprises tail samples of the first sample block,
• forming a second sample block comprising header samples followed by the second sample sub-sequence, wherein the header samples correspond to the tail samples,
• demodulating the first sample block by a first digital demodulator, so as to produce a first symbol block,
• demodulating the second sample block by a second digital demodulator independent of the first digital demodulator so as to produce a second symbol block, the second digital demodulator implementing a carrier and/or symbol rate synchronization, and taking as input the second sample block starting with the header samples, the header samples comprising synchronization samples in a suitable number for the synchronization to be effective before the second digital demodulator starts to demodulate the second sample sub-sequence,
• reconstructing an output symbol sequence by concatenating a symbol sequence coming from the first symbol block with a symbol sequence coming from the second symbol block.

A device comprising:

• a distributor configured to
• receive a sequence of digital signal samples coming from at least one modulated analog signal, the sequence of digital signal samples comprising a first sample sub-sequence and a second sample sub-sequence different from the first sample sub-sequence,
• form a first sample block comprising the first sample sub-sequence, wherein the first sample sub-sequence comprises tail samples of the first sample block,
• form a second sample block comprising header samples followed by the second sample sub-sequence, wherein the header samples correspond to the tail samples,
• a first digital demodulator configured to demodulate the first sample block so as to produce a first symbol block,
• a second digital demodulator independent of the first digital demodulator and configured to demodulate the second sample block so as to produce a second symbol block, the second digital demodulator being configured to implement a carrier and/or symbol rate synchronization, and to take as input the second sample block starting with the header samples, the header samples comprising synchronization samples in a suitable number for the synchronization to be effective before the second digital demodulator starts to demodulate the second sample sub-sequence,
• a reconstructing module configured to reconstruct an output symbol sequence by concatenating a symbol sequence coming from the first symbol block with a symbol sequence coming from the second block.