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US 2021/0175901 A1Published application
Hybrid ldpc decoder with mixed precision components
AssigneeIntel Corporation
InventorsDebarnab Mitra, Santhosh K. Vanaparthy
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Abstract
An embodiment of an electronic apparatus may comprise one or more substrates, and a decoder coupled to the one or more substrates, the decoder including logic to perform a first decode stage with a first fixed quantization width, and perform a second decode stage with a second fixed quantization width that is different from the first fixed quantization width. Other embodiments are disclosed and claimed.
Claims20
An electronic apparatus, comprising:
- one or more substrates;
- and
- a decoder coupled to the one or more substrates, the decoder including logic to:
- perform a first decode stage with a first fixed quantization width, and
- perform a second decode stage with a second fixed quantization width that is different from the first fixed quantization width.
2 more elements
An electronic system, comprising:
- a controller;
- memory;
- and
- a decoder communicatively coupled to the controller and the memory, the decoder including logic to:
- perform a first decode stage with a first fixed quantization width, and
- perform a second decode stage with a second fixed quantization width that is different from the first fixed quantization width.
3 more elements
A method of decoding parity information, comprising:
- performing a first decode stage of a decoder with a first fixed quantization width;
- and
- performing a second decode stage of the decoder with a second fixed quantization width that is different from the first fixed quantization width.
Dependencies are inferred from the claim text.