Calibrating Resistance for Data Drivers

A method for operating a data transmitter circuit, the method comprising:

• receiving a differential data signal at a plurality of driver slices;
• at a first bias circuit, maintaining an output resistance of a first signal generator circuit of a first driver slice to a first resistance value, including biasing a first transistor of the first signal generator circuit;
• and
• driving the differential data signal onto a transmission line by the first signal generator circuit.

A semiconductor chip comprising:

• a driver circuit including a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit and a second signal generator circuit;
• a first bias circuit replicating the first signal generator circuit, the first bias circuit coupled to a first p-type metal oxide semiconductor (PMOS) transistor of the first signal generator circuit and coupled to a second PMOS transistor of the first signal generator circuit;
• and
• a second bias circuit replicating the second signal generator circuit, the second bias circuit coupled to a first n-type metal oxide semiconductor (NMOS) transistor of the second signal generator circuit and coupled to a second NMOS transistor of the second signal generator circuit.

A data transmitter in a semiconductor chip, the data transmitter comprising:

• a plurality of driver slices coupled in parallel to a serial data output, each one of the driver slices including:
• first means for driving a first portion of a differential data signal;
• and second means for driving a second portion of the differential data signal;
• and
• means for matching an output resistance of the data transmitter to a resistance of a transmission line, the matching means including:
• a first bias circuit replicating a first portion of the first means, the first bias circuit coupled to a first p-type metal oxide semiconductor (PMOS) transistor of the first portion of the first means and coupled to a second PMOS transistor of the first portion of the first means;
• and
• a second bias circuit replicating a second portion of the first means, the second bias circuit coupled to a first n-type metal oxide semiconductor (NMOS) transistor of the second portion of the first means and coupled to a second NMOS transistor of the second portion of the first means.