Ic chip
AssigneeNippon Telegraph and Telephone Corporation
InventorsMunehiko NAGATANI, Hideyuki NOSAKA, Shinsuke NAKANO
Life of this patent
Estimating the term…
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AssigneeNippon Telegraph and Telephone Corporation
InventorsMunehiko NAGATANI, Hideyuki NOSAKA, Shinsuke NAKANO
Estimating the term…
A reception-side IC chip (1a) includes a pad (15) which is connected to a transmission line (2) which is outside the chip and has a characteristic impedance Z0 of 50 Ω, a signal line (16), one end of which is connected to the pad (15), a reception-side input unit circuit (10) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line (2), a 50-Ω termination resistor (11), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line (16) and is configured to terminate the transmission line (2), and a capacitor (12) inserted between a node (A) of the signal line (16) and the termination resistor (11) and an input terminal (In) of the reception-side input unit circuit (10). A DC-blocking circuit is formed by the capacitor (12).
An IC chip comprising:
Dependencies are inferred from the claim text.