Resistive random access memory integrated under a vertical field effect transistor

A semiconductor structure comprising:

• a vertical field effect transistor, the vertical field effect transistor comprising a top source drain, a bottom source drain, and an epitaxial channel;
• and
• a resistive random access memory below the vertical field effect transistor, the resistive random access memory comprising a top electrode and a bottom electrode separated by an epitaxial oxide layer, wherein the top electrode, which functions as the bottom source drain of the vertical field effect transistor, is in direct contact with the epitaxial channel of the vertical field effect transistor, wherein the top electrode extends downward into the bottom electrode.

A method of forming a semiconductor structure, the method comprising:

• forming a vertical field effect transistor, the vertical field effect transistor comprising a top source drain, a bottom source drain, and an epitaxial channel;
• and
• forming a resistive random access memory below the vertical field effect transistor, the resistive random access memory comprising an epitaxial oxide layer, a top electrode, and a bottom electrode, wherein the top electrode is in direct contact with the epitaxial channel of the vertical field effect transistor.