Nonvolatile memory devicee
AssigneeSamsung Electronics Co., Ltd.
InventorsDONGHA SHIN, YOHAN LEE
Life of this patent
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Abstract
A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.
Claims20
A nonvolatile memory device comprising:
- a memory cell area including at least one cell structure and a common source plate;
- a peripheral circuit area on which the memory cell area is mounted,
- including a buried area covered by the memory cell area and a first exposed area uncovered by the memory cell area;
- a first peripheral circuit (PC) via extending from the first exposed area;
- and
- a first common source (CS) via extending from the common source plate,
- wherein the first PC via and the first CS via are connected by a first wire disposed outside the at least one cell structure that provides a bias voltage to the common source plate.
A nonvolatile memory device comprising:
- a memory cell area including a cell structure and a common source plate, and mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area;
- a first peripheral circuit (PC) via extending from the exposed area;
- and
- a common source (CS) via extending from the common source plate,
- wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.
A nonvolatile memory device comprising:
- a memory cell array including a plurality of cell strings disposed on a common source plate;
- and
- a peripheral circuit having an upper surface on which the memory cell array is mounted,
- wherein the peripheral circuit includes:
- a first row decoder having a first upper surface uncovered by the memory cell array, and configured to bias the plurality of cell strings through first wires extending upward from the first upper surface;
- a second row decoder having a second upper surface uncovered by the memory cell array, and configured to bias the plurality of cell strings through second wires extending upward from the second upper surface;
- first common source switches having a third upper surface uncovered by the memory cell array, and configured to bias the common source plate through third wires extending upward from the third upper surface;
- and
- second common source switches having a fourth upper surface uncovered by the memory cell array, and configured to bias the common source plate through fourth wires extending upward from the fourth upper surface.
Dependencies are inferred from the claim text.