Selective recess of interconnects for probing hybrid bond devices

A system, comprising:

• a microprocessor;
• and
• a memory coupled to the microprocessor, wherein at least one of the memory or the microprocessor comprises a first integrated circuit (IC) die comprising a first dielectric and a plurality of adjacent first interconnect structures;
• and
• a second IC die comprising a second dielectric and a plurality of adjacent second interconnect structures, wherein a first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components, and wherein a second of the first interconnect structures is set back a distance from a plane of the bond interface.

A method for making an IC device, comprising:

• forming a plurality of adjacent first interconnect structures within a first dielectric of a first component;
• recessing a first of the first interconnect structures below a surface of the first dielectric that is planar with a second of the first interconnect structures;
• and
• bonding the first component to a second component wherein the second component comprises a plurality of second interconnect structures within a second dielectric, and wherein a bond interface is formed between the second of the first interconnect structures and a first of the second interconnect structures, and wherein the first of the first interconnect structures is set back from the plane of the bond interface.