Heterogenous Integration for RF, Microwave and MM Wave Systems in Photoactive Glass Substrates

A package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass made by a method comprising:

• forming a spacer by:
• exposing at least one portion of the photosensitive glass substrate with an activating energy source;
• heating the photosensitive glass substrate for at least ten minutes above its glass transition temperature;
• cooling the photosensitive glass substrate to transform at least a part of the exposed glass to a crystalline material to form a glass-crystalline substrate;
• etching the glass-crystalline substrate with an etchant solution to form one or more channels or vias in the glass-crystalline substrate, wherein the glass-crystalline substrate adjacent to the trenches or vias, which may optionally be converted to a ceramic phase;
• depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate exposed during the etching step to enable electroplating of copper to fill the trenches on the surface or in the vias of the spacer;
• and
• connecting a high electron mobility transistor (HEMT) or other active device to a copper plate or copper ground plate via the spacer wafer;
• wherein the spacer reduces a parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device.

A method for creating a system in a package with integrated lumped element devices formed as a system-in-package (SiP) in or on photo-definable glass comprising the steps of:

• masking a design layout comprising one or more structures to form one or more electrical components on or in a photosensitive glass substrate spacer;
• transforming at least a part of the exposed glass to a crystalline material to form a glass-crystalline substrate;
• etching the glass-crystalline substrate with an etchant solution to form one or more channels or vias in the glass-crystalline substrate, which may optionally be converted to a ceramic phase;
• depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate exposed during the etching step to enable electroplating of copper to fill the vias and deposit on the surface of the photodefinable glass;
• and
• placing and electrically connecting a high electron mobility transistor (HEMT) or other active device on the copper plate or copper-coated glass wafer across the photosensitive glass substrate spacer;
• wherein the integrated lumped element devices reduces the parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device.

A method for creating a system in a package with integrated lumped element devices formed as a heterogeneous integration system-on-chip (HiSoC) using photo-definable glass comprising the steps of:

• forming an integrated passive device (IPD) wafer by:
• obtaining a copper plate/substrate
• coating the copper plate/substrate with a photoresist in an alignment pattern for one or more dies;
• using the alignment marks to pick, place and bond an active device to the copper plate/substrate;
• depositing solder bonding balls on one or more contact pads of the active device;
• forming a spacer wafer by:
• lap and polish a spacer wafer of photodefinable glass;
• exposing, baking and etching one or more through hole openings or through hole vias to provide an electrical connection through the spacer wafer;
• depositing a seed layer of Ti/Cu by chemical vapor deposition (CVD) on the spacer wafer;
• electroplating or electroless plating copper into the through hole openings or the through hole vias in the spacer wafer;
• removing excess cooper to reduce a thickness of the copper on the spacer wafer;
• coating, exposing and developing a photoresist in a pattern on a first side of the spacer wafer, wherein the pattern has a spacer edge area that is smaller than the pattern on the spacer wafer;
• coating the first side of the spacer wafer with an electrically conductive material with a sputter deposition system;
• removing the photoresist to leave the electrically conductive material in a continuous pattern;
• uniformly coating a second side of the spacer wafer with an electrically conductive material using a sputter deposition system;
• aligning the spacer wafer on the copper substrate with the alignment marks;
• bonding the spacer and to the copper substrate;
• depositing solder ball on an opposite side of the spacer wafer at the one or more through hole opening or through hole vias;
• and
• using the alignment marks to electrically connect the integrated passive device (IPD) wafer to the spacer wafer with solder balls to connect to the active device to a ground.