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US 2021/0175128 A1Published application
Method of making 3d cmos with integrated channel and s/d regions
AssigneeTokyo Electron Limited
InventorsMark I. GARDNER, H. Jim FULFORD
Life of this patent
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Abstract
Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can enable higher density circuits to be produced at reduced cost. The methods can include growth of channel regions and S/D regions for NMOS devices using a first same nano-sheet in a nano-sheet stack. Similarly, the methods can include growth of channel regions and S/D regions for PMOS devices using a second same nano-sheet in the nano-sheet stack. The resulting 3D CMOS stack can include integrated channel and S/D regions.
Claims20
A method of fabricating a semiconductor device, comprising:
- forming a nano-sheet stack on a surface of a substrate, the nano-sheet stack including
- a first portion formed from a first channel material and disposed proximal to the substrate, the first channel material being doped with a first dopant, and the first portion including at least one layer of the first channel material,
- a second portion formed from a second channel material and disposed vertically above the first portion, the second channel material being doped with a second dopant, and the second portion including at least one layer of the second channel material, and
- a bulk portion formed from a bulk material and disposed between the first portion and the second portion;
- etching the nano-sheet stack to form multilayer sub-stacks, each stack of the multilayer sub-stacks including the first portion having uncovered sidewalls of the first channel material and the second portion having uncovered sidewalls of the second channel material;
- growing a first source/drain region in the first portion, the first source/drain region being doped based on the first dopant;
- and
- growing a second source/drain region in the second portion, the second source/drain region being doped based on the second dopant.
5 more elements
A method of fabricating a semiconductor device, comprising:
- forming a nano-sheet stack on a surface of a substrate, the nano-sheet stack including
- a first portion formed from a first channel material and disposed proximal to the substrate, the first channel material being doped with a first dopant, and the first portion including at least one layer of the first channel material,
- a second portion formed from a second channel material and disposed vertically above the first portion, the second channel material being doped with a second dopant, and the second portion including at least one layer of the second channel material, and
- a bulk portion formed from a bulk material and disposed between the first portion and the second portion;
- depositing a mask overtop the nano-sheet stack;
- etching the nano-sheet stack to form multilayer sub-stacks defined by the mask, each stack of the multilayer sub-stacks including the first portion having uncovered sidewalls of the first channel material and the second portion having uncovered sidewalls of the second channel material;
- growing a first source/drain region at ends of the first channel material in the first portion, the first source/drain region being doped based on the first dopant;
- growing a second source/drain region at ends of the second channel material in the second portion, the second source/drain region being doped based on the second dopant;
- forming a first gate stack on the first source/drain region at ends of the first channel material in the first portion, the first gate stack including at least one layer of a first gate material;
- forming a second gate stack on the second source/drain region at ends of the second channel material in the second portion, the second gate stack including at least one layer of a second gate material;
- depositing an organic planarization layer to at least cover the first gate stack on the first source/drain region;
- and
- recessing the organic planarization layer to uncover the second gate stack on the second source/drain region.
10 more elements
Dependencies are inferred from the claim text.