Memory system, integrated circuit system, and operation method of memory system

An integrated circuit system comprising a first device, a second device and a third device,

• wherein the first device is suitable for transmitting upstream data and a first Error Correction Code (ECC) corresponding to the upstream data during an upstream operation,
• wherein the second device comprises:
• a first error correction circuit suitable for correcting an error within the transmitted upstream data when the error is detected within the transmitted upstream data, through the transmitted first ECC;
• and
• a second ECC generation circuit suitable for generating a second ECC based on the transmitted upstream data when an error is not detected within the transmitted upstream data or the error-corrected upstream data when the error is corrected within the transmitted upstream data,
• wherein the third device receives the generated second ECC and the transmitted upstream data or the error-corrected upstream data.

An operation method of a memory system, comprising:

• transmitting, by a memory controller, write data and a first Error Correction Code (ECC) corresponding to the write data to a module controller;
• performing, by the module controller, a first operation of generating a second ECC based on the transmitted write data;
• finding and correcting, by the module controller, an error within the transmitted write data through the first ECC;
• canceling the first operation in response to the found error;
• performing, by the module controller, a second operation of generating the second ECC based on the error-corrected write data;
• and
• transmitting, by the module controller, the generated second ECC and the error-corrected write data to one or more memories.

A memory system comprising:

• a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation;
• a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected;
• a second ECC generation circuit suitable for generating a second write ECC using the write data outputted from the first error correction circuit;
• and
• one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC,
• wherein the second write ECC has an error correction ability superior to that of the first write ECC.

An operating method of a controller, the operating method comprising:

• error-decoding write data through a first error correction code, the write data being provided with the first error correction code;
• error-encoding, when the provided write data is not error-corrected during the error-decoding of the provided write data, the provided write data to generate a second error correction code;
• error-encoding, when the provided write data is error-corrected during the error-decoding of the provided write data, the error-corrected write data to generate a third error correction code;
• and
• controlling a memory device to store therein a pair of the provided write data and the second error correction code or a pair of the error-corrected write data and the third error correction code.