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US 2021/0174890 A1Published application
Test circuit and memory chip using test circuit
AssigneeChangxin Memory Technologies, Inc.
InventorsJia WANG, Liang ZHANG, Hongwen LI
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AssigneeChangxin Memory Technologies, Inc.
InventorsJia WANG, Liang ZHANG, Hongwen LI
Estimating the term…
Embodiments provide a test circuit and a memory chip. The test circuit is configured to read compressed data of a memory. The test circuit includes M storage blocks, wherein the M is an even number greater than or equal to 2. N storage blocks constitute one storage group, wherein the N is an even number greater than or equal to 2 and less than or equal to the M, and the M is an integral multiple of the N. The test circuit further includes a compressed data reading unit. One compressed data reading unit corresponds to one storage group. The compressed data reading unit is connected to the N storage blocks in the corresponding storage group. The compressed data reading unit receives a compressed data reading command and address information, and reads data in the N storage blocks according to the compressed data reading command and the address information.
A test circuit for reading compressed data of a memory, wherein the test circuit comprises M storage blocks divided into multiple storage groups, wherein M is an even number ≥2;
A memory chip, comprising a data read-write bus and a test circuit, wherein the test circuit comprises M storage blocks divided into multiple storage groups, wherein M is an even number ≥2;
Dependencies are inferred from the claim text.