US 2021/0174882 A1Published application

Output circuit

AssigneeKioxia Corporation

InventorsYousuke HAGIWARA, Kensuke YAMAMOTO, Takeshi HIOKA, Satoshi INOUE

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Abstract

In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

Claims20

Dependent claims

An output circuit comprising:

a first power supply line;
a second power supply line;
a third power supply line;
a pad;
a first transistor with a first end being coupled to the first power supply line, and a second end being coupled to the pad;
a second transistor with a first end being coupled to the second power supply line, and a second end being coupled to the pad;
and
a first circuit coupled to each of the third power supply line and a gate of the first transistor,
wherein
a first voltage is applied to the first power supply line,
a second voltage which is lower than the first voltage is applied to the second power supply line,
a third voltage which is different from both the first and second voltages is applied to the third power supply line, and
wherein
in a first case, the first circuit applies a fourth voltage to the gate of the first transistor, and
in a second case, the first circuit causes the third power supply line and the gate of the first transistor to be electrically non-coupled.

12 more elements

An output circuit comprising:

a first power supply line;
a second power supply line;
a third power supply line;
a pad;
a first transistor with a first end being coupled to the first power supply line, and a second end being coupled to the pad;
a second transistor with a first end being coupled to the second power supply line, and a second end being coupled to the pad;
and
a first circuit coupled to each of the third power supply line and a gate of the second transistor,
wherein
a first voltage is applied to the first power supply line,
a second voltage which is lower than the first voltage is applied to the second power supply line,
a third voltage which is different from both the first and second voltages is applied to the third power supply line, and
wherein
in a first case, the first circuit applies a fourth voltage to the gate of the second transistor, and
in a second case, the first circuit causes the third power supply line and the gate of the second transistor to be electrically non-coupled.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/017,726Filed 11 Sep 2020
Priority: JP 2019-2195804 Dec 2019
Published: 10 Jun 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits
G11C 16/0441
Comprising cells containing floating gate transistors: comprising cells containing multiple floating gate devices, e.g. separate read-and-write…
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits

Family

US 11,380,406 B2Related patent
US 2021/0174882 A1This patent

From the US filing history. Foreign family members aren’t listed.

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