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US 2021/0174879 A1Published application
Semiconductor memory device
AssigneeKioxia Corporation
InventorsTakeshi HIOKA, Naofumi ABIKO, Masaki UNNO
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AssigneeKioxia Corporation
InventorsTakeshi HIOKA, Naofumi ABIKO, Masaki UNNO
Estimating the term…
A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.
A semiconductor memory device comprising:
A method of erasing data stored in a first memory cell of a semiconductor memory device that includes a first memory block including the first memory cell, a second memory block including a second memory cell, a source line, a bit line, a first select transistor in the first memory block having a first end connected to a plurality of memory cells including the first memory cell and a second end connected to the source line, a second select transistor in the first memory block having a first end connected to the plurality of memory cells and a second end connected to the bit line, and a third select transistor in the second memory block having a first end connected to the bit line through a plurality of memory cells including the second memory cell and a second end connected to the source line, said method comprising:
Dependencies are inferred from the claim text.