Semiconductor memory system including a plurality of semiconductor memory devices
AssigneeToshiba Memory Corporation
InventorsNoboru SHIBATA, Hiroshi SUKEGAWA
Life of this patent
Estimating the term…
Abstract
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
Claims13
(canceled)
A semiconductor memory system comprising:
- a first semiconductor memory device;
- a second semiconductor memory device;
- and
- a first common signal line connected to the first semiconductor memory device and the second semiconductor memory device,
- wherein the first semiconductor memory device and the second semiconductor memory device operate based on a signal on the first common signal line.
A method for controlling a semiconductor memory system,
- the system comprising:
- a first semiconductor memory device;
- a second semiconductor memory device;
- and
- a first common signal line connected to the first semiconductor memory device and the second semiconductor memory device,
- the method comprising:
- causing the first semiconductor memory device and the second semiconductor memory device to operate based on a clock signal on the first common signal line.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series;
- a first terminal externally connected to another semiconductor memory device and a controller device via a first common signal line, and being supplied with a clock signal;
- and
- a second terminal externally connected to the another semiconductor memory device and the controller device via a second common signal line, and being supplied with a control signal.
Dependencies are inferred from the claim text.