Fractional program commands for memory devices

A Flash memory device, comprising:

• Flash memory cells;
• a circuit to receive fractional program commands, the circuit receiving an address specifying a group of the Flash memory cells for a program operation in accordance with the fractional program commands, the circuit responsive to a first one of the fractional program commands to
• apply a first fractional program pulse to program first data in the group of the Flash memory cells;
• verify whether the first fractional program pulse completely programmed the first data in the group of Flash memory cells;
• generate verification data indicating a result of the verify;
• and
• wherein the circuit is responsive to a subsequent fractional program command to selectively apply a second fractional program pulse to program the first data in the group of Flash memory cells based on the verification data.

A method of operation in a Flash memory device, the method comprising:

• receiving, via a circuit, fractional program commands and an address specifying a group of Flash memory cells for a program operation in accordance with the fractional program commands;
• executing a first one of the fractional program commands by
• applying a first fractional program pulse to program first data in the group of the Flash memory cells;
• verifying whether the first fractional program pulse completely programmed the first data in the group of Flash memory cells;
• generating verification data indicating a result of the verifying;
• and
• executing a subsequent fractional program command to selectively apply a second fractional program pulse to program the first data in the group of Flash memory cells based on the verification data.

A device, comprising:

• a circuit to execute fractional program commands for a program operation directed to an addressed group of Flash memory cells, the circuit responsive to a first one of the fractional program commands to
• apply a first fractional program pulse to program first data in the addressed group of Flash memory cells;
• verify whether the first fractional program pulse completely programmed the first data in the addressed group of Flash memory cells;
• generate verification data indicating a result of the verify;
• and
• wherein the circuit is responsive to a subsequent fractional program command to selectively apply a second fractional program pulse to program the first data based on the verification data.