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AssigneeMediaTek Singapore Pte. Ltd.
InventorsChetan Deshpande, Gajanan Sahebrao Jedhe, Ritesh Garg, Gaurang Prabhakar Narvekar, Yi-Wei Chen
Estimating the term…
Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.
A memory device comprising:
A memory device comprising:
A method for controlling a memory device comprising a plurality of rows of memory cells, wherein a first row of the plurality of rows comprises a first segment and a second segment, the first segment comprises a first subset of the memory cells of the first row and the second segment comprises a second subset of the memory cells of the first row, the method comprising:
Dependencies are inferred from the claim text.