Semiconductor memory device

A semiconductor memory device comprising:

• a substrate including a main surface extending in a first direction and a second direction that intersects the first direction;
• a first memory cell array including a first conductive layer, a second conductive layer, a third conductive layer, a first memory cell, and a second memory cell, wherein,
• the first conductive layer is arranged on one side of a third direction that intersects the first direction and the second direction of the substrate, and extends in the first direction,
• the second conductive layer is arranged on the one side of the third direction of the first conductive layer and extends in the second direction,
• the third conductive layer is arranged on the one side of the third direction of the second conductive layer and extends in the first direction,
• the first memory cell is arranged between the first conductive layer and the second conductive layer with respect to the third direction, and
• the second memory cell is arranged between the second conductive layer and the third conductive layer with respect to the third direction;
• a second memory cell array including a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a third memory cell, and a fourth memory cell, wherein
• the fourth conductive layer is arranged on the one side of the third direction of the substrate and extends in the first direction,
• the fifth conductive layer is arranged on the one side of the third direction of the fourth conductive layer and extends in the second direction,
• the sixth conductive layer is arranged on the one side of the third direction of the fifth conductive layer and extends in the first direction,
• the third memory cell is arranged between the fourth conductive layer and the fifth conductive layer with respect to the third direction, and
• the fourth memory cell is arranged between the fifth conductive layer and the sixth conductive layer with respect to the third direction;
• a first driver that applies a voltage to the first conductive layer and the fourth conductive layer;
• a second driver that applies a voltage to the third conductive layer and the sixth conductive layer;
• a first connection arranged between the first memory cell array and the second memory cell array with respect to the first direction, and extending in the third direction, the first connection electrically coupling the first conductive layer and the fourth conductive layer to the first driver;
• and
• a second connection arranged between the first memory cell array and the second memory cell array with respect to the first direction, and extending in the third direction, the second connection electrically coupling the third conductive layer and the sixth conductive layer to the second driver.