Resistive memory device
AssigneeSamsung Electronics Co., Ltd.
InventorMAKOTO HIRANO
Life of this patent
Estimating the term…
Abstract
A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.
Claims22
A resistive memory device comprising:
- a first bit line group including a first edge bit line;
- a second bit line group including a second edge bit line;
- and
- a first boundary transistor configured to apply a non-selection voltage to the second edge bit line when the first edge bit line is selected,
- wherein the first edge bit line is disposed closest to the second bit line group among the first bit line group, and the second edge bit line is disposed closest to the first bit line group among the second bit line group.
4-5. (canceled)
A resistive memory device comprising:
- a first bit line group including a first edge bit line;
- a second bit line group including a second edge bit line;
- a first edge transistor configured to apply a selection voltage to the first edge bit line according to a first selection signal;
- a second edge transistor configured to apply the selection voltage to the second edge bit line according to a second selection signal;
- a third edge transistor configured to apply a non-selection voltage to the first edge bit line according to the first selection signal;
- and
- a fourth edge transistor configured to apply the non-selection voltage to the second edge bit line according to the second selection signal.
A registive memory device comprising:
- a first word line group including a first edge word line;
- a second word line group including a second edge word line;
- a first boundary transistor configured to, when the first edge word line is selected, apply a non-selection voltage to the second edge word line;
- and
- a second boundary transistor configured to, when the second edge word line is selected, apply the non-selection voltage to the first edge word line,
- wherein the first edge word line is disposed closest to the second word line group among the first word line group, and the second edge word line is disposed closest to the first word line group among the second word line group.
23-73. (canceled)
Dependencies are inferred from the claim text.