Memory Device Implementing Multiple Port Read

A method of operating a memory device, comprising:

• at an array of bitcells including a plurality of rows of bitcells, each bitcell of the array including a write wordline port and a first read wordline port:
• in a write mode, transmitting a write wordline signal to the write wordline port and disabling a second read wordline port external to the array of bitcells;
• and
• in a read mode, transmitting a second read wordline signal to the write wordline signal via the second read wordline port.

A memory device, comprising:

• an array of bitcells including a plurality of rows of bitcells, each bitcell of the array including a write wordline port and a first read wordline port;
• means for, in a write mode, transmitting a write wordline signal to the write wordline port and disabling a second read wordline port external to the array of bitcells;
• and
• means for, in a read mode, transmitting a second read wordline signal to the write wordline signal via the second read wordline port.