Memory and memory system
AssigneeSK hynix Inc.
InventorsHoiju CHUNG, Paul FAHEY
Life of this patent
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Abstract
A memory includes a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller.
Claims20
A memory comprising:
- a plurality of rows, each of which is coupled to a plurality of memory cells;
- a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row;
- and
- a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller.
A memory system comprising:
- a memory controller;
- and
- a memory,
- wherein the memory includes:
- a plurality of rows, each of which is coupled to a plurality of memory cells;
- a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row;
- and
- a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller, wherein the memory controller is suitable for transferring a command for refreshing the target rows to the memory when the information is received from the memory.
A memory system comprising:
- a memory controller;
- and
- a memory,
- wherein the memory includes:
- a plurality of rows, each of which is coupled to a plurality of memory cells;
- a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row;
- and
- a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller,
- wherein the memory controller is suitable for applying no command to the memory in a predetermined period after the information is received from the memory.
A method for operating a memory system including a memory controller and a memory, the method comprising:
- determining, by the memory, a row that is likely to lose data among a plurality of rows as a target row;
- determining, by the memory, whether a number of target rows reaches a threshold value or not;
- and
- transferring, by the memory, information representing that the number of the target rows reaches the threshold value to the memory controller.
A method for operating a memory, the method comprising:
- determining, as a target row, a neighboring row disposed adjacent to a row with excessive activation times;
- checking whether a number of target rows reaches a threshold value or not;
- informing a memory controller when the number of the target rows reaches the threshold value;
- and
- performing a refresh operation on the target rows.
Dependencies are inferred from the claim text.