Inversion signal generation circuit

An inversion signal generation circuit comprising:

• a transition detection signal generation circuit suitable for generating first to eighth transition detection signals using first to eighth phase data each including multi-bit data;
• a first XOR gate suitable for receiving an eighth inversion signal and the first transition detection signal, and generating a first pre-inversion signal;
• a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal;
• a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal;
• a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal;
• a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal;
• a sixth XOR gate suitable for receiving the fourth transition detection signal and the fifth transition detection signal;
• a seventh XOR gate suitable for receiving the third pre-inversion signal and an output signal of the sixth XOR gate, and generating a fifth pre-inversion signal;
• an eighth XOR gate suitable for receiving the output signal of the sixth XOR gate and the sixth transition detection signal;
• a ninth XOR gate suitable for receiving the third pre-inversion signal and an output signal of the eighth XOR gate, and generating a sixth pre-inversion signal;
• a tenth XOR gate suitable for receiving the sixth transition detection signal and the seventh transition detection signal;
• an eleventh XOR gate suitable for receiving the output signal of the sixth XOR gate and an output signal of the tenth XOR gate;
• a twelfth XOR gate suitable for receiving the third pre-inversion signal and an output signal of the 11th XOR gate, and generating a seventh pre-inversion signal;
• a thirteenth XOR gate suitable for receiving the seventh pre-inversion signal and the eighth transition detection signal, and generating an eighth pre-inversion signal;
• and
• a first alignment circuit suitable for generating first to seventh inversion signals and the eighth inversion signal by aligning the first to eighth pre-inversion signals.

An operating method of a circuit, the operating method comprising:

• generating first to fourth transition detection signals based on first to fourth phase data each including multi-bit data;
• generating a first pre-inversion signal through a XOR operation on a fourth inversion signal and the first transition detection signal;
• generating a second pre-inversion signal through a XOR operation on the first pre-inversion signal and the second transition detection signal;
• generating an intermediate signal through a XOR operation on the second transition detection signal and the third transition detection signal;
• generating a third pre-inversion signal through a XOR operation on the first pre-inversion signal and the intermediate signal;
• generating a fourth pre-inversion signal through a XOR operation on the third pre-inversion signal and the fourth transition detection signal;
• and
• generating first to third inversion signals and the fourth inversion signal by aligning the first to fourth pre-inversion signals.

An operating method of a circuit, the operating method comprising:

• generating first to eighth transition detection signals based on first to eighth phase data each including multi-bit data;
• generating a first pre-inversion signal through a XOR operation on an eighth inversion signal and the first transition detection signal;
• generating a second pre-inversion signal through a XOR operation on the first pre-inversion signal and the second transition detection signal;
• generating a first intermediate signal through a XOR operation on the second transition detection signal and the third transition detection signal;
• generating a third pre-inversion signal through a XOR operation on the first pre-inversion signal and the first intermediate signal;
• generating a fourth pre-inversion signal through a XOR operation on the third pre-inversion signal and the fourth transition detection signal;
• generating a second intermediate signal through a XOR operation on the fourth transition detection signal and the fifth transition detection signal;
• generating a fifth pre-inversion signal through a XOR operation on the third pre-inversion signal and the second intermediate signal;
• generating a third intermediate signal through a XOR operation on the second intermediate signal and the sixth transition detection signal;
• generating a sixth pre-inversion signal through a XOR operation on the third pre-inversion signal and the third intermediate signal;
• generating a fourth intermediate signal through a XOR operation on the sixth transition detection signal and the seventh transition detection signal;
• generating a fifth intermediate signal through a XOR operation on the second intermediate signal and the fourth intermediate signal;
• generating a seventh pre-inversion signal through a XOR operation on the third pre-inversion signal and the fifth intermediate signal;
• generating an eighth pre-inversion signal through a XOR operation on the seventh pre-inversion signal and the eighth transition detection signal;
• and
• generating first to seventh inversion signals and the eighth inversion signal by aligning the first to eighth pre-inversion signals.