Display driver and display device

A display driver that captures a plurality of pixel data pieces based on a video signal and according to a load signal and generates a plurality of pixel drive voltages to be applied to a plurality of source lines of a display panel according to the plurality of captured pixel data pieces, the display driver comprising:

• first and second bus wiring each constituted by a plurality of wiring lines;
• a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations (M is an integer of 2 or more), applies the M gradation voltages to an intermediate portion between one end and the other end of each of M wiring lines belonging to the first bus wiring, and applies the M gradation voltages to an intermediate portion between one end and the other end of each of M wiring lines belonging to the second bus wiring;
• first to rth decoders (r is an integer of 2 or more) which are disposed side by side along the first bus wiring, and each of which receives the M gradation voltages via the M wiring lines belonging to the first bus wiring and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage;
• (r+1)th to nth decoders which are disposed side by side along the second bus wiring, and each of which receives the M gradation voltages via the M wiring lines belonging to the second bus wiring and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage;
• output amplifiers that individually amplify the voltages output from the first to rth decoders and the (r+1)th to nth decoders and generate the amplified voltages as n pixel drive voltages;
• a first inter-gradation short circuit that short-circuits one ends of each of the M wiring lines belonging to the first bus wiring according to the load signal;
• a second inter-gradation short circuit that short-circuits the other ends of each of the M wiring lines belonging to the first bus wiring according to the load signal;
• a third inter-gradation short circuit that short-circuits one ends of each of the M wiring lines belonging to the second bus wiring according to the load signal;
• and
• a fourth inter-gradation short circuit that short-circuits the other ends of each of the M wiring lines belonging to the second bus wiring according to the load signal.

A display driver that captures a plurality of pixel data pieces based on a video signal and according to a load signal and generates a plurality of pixel drive voltages to be applied to a plurality of source lines of a display panel according to the plurality of captured pixel data pieces, the display driver comprising:

• bus wiring constituted by M wiring lines (M is an integer of 2 or more);
• a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with gradations, and applies the M gradation voltages to a portion between one end and the other end of each of the M wiring lines;
• a plurality of decoders which is disposed side by side along the M wiring lines, and each of which receives the M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage;
• a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages;
• and
• an inter-gradation short circuit that short-circuits at least one of the one ends and the other ends of each of the M wiring lines according to the load signal.

A display device which includes a display panel that has a plurality of source lines, and a display driver that captures a plurality of pixel data pieces based on a video signal and according to a load signal and generates a plurality of pixel drive voltages according to the plurality of captured pixel data pieces to apply each pixel drive voltage to the plurality of source lines of the display panel,

• wherein the display driver includes
• bus wiring constituted by a plurality of wiring lines;
• a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations (M is an integer of 2 or more), and applies the M gradation voltages to an intermediate portion between one end and the other end of each of M wiring lines belonging to the bus wiring;
• a plurality of decoders which is disposed side by side along the M wiring lines, and each of which receives the M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage;
• a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages;
• a first inter-gradation short circuit that short-circuits one ends of each of the M wiring lines according to the load signal;
• and
• a second inter-gradation short circuit that short-circuits the other ends of each of the M wiring lines according to the load signal.

A display device which includes a display panel that has a plurality of source lines, and a display driver that captures a plurality of pixel data pieces based on a video signal and according to a load signal and generates a plurality of pixel drive voltages according to the plurality of captured pixel data pieces to apply each pixel drive voltage to the plurality of source lines of the display panel,

• wherein the display driver includes
• first and second bus wiring each constituted by a plurality of wiring lines;
• a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations (M is an integer of 2 or more), applies the M gradation voltages to an intermediate portion between one end and the other end of each of M wiring lines belonging to the first bus wiring, and applies the M gradation voltages to an intermediate portion between one end and the other end of each of M wiring lines belonging to the second bus wiring;
• first to rth decoders (r is an integer of 2 or more) which are disposed side by side along the first bus wiring, and each of which receives the M gradation voltages via the M wiring lines belonging to the first bus wiring and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage;
• (r+1)th to nth decoders which are disposed side by side along the second bus wiring, and each of which receives the M gradation voltages via the M wiring lines belonging to the second bus wiring and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage;
• output amplifiers that individually amplify the voltages output from the first to rth decoders and the (r+1)th to nth decoders and generate the amplified voltages as n pixel drive voltages;
• a first inter-gradation short circuit that short-circuits one ends of each of the M wiring lines belonging to the first bus wiring according to the load signal;
• a second inter-gradation short circuit that short-circuits the other ends of each of the M wiring lines belonging to the first bus wiring according to the load signal;
• a third inter-gradation short circuit that short-circuits one ends of each of the M wiring lines belonging to the second bus wiring according to the load signal;
• and
• a fourth inter-gradation short circuit that short-circuits the other ends of each of the M wiring lines belonging to the second bus wiring according to the load signal.