Memory control method and system

A system, comprising:

• a memory architecture, including
• one or more accelerators, a respective accelerator of the one or more accelerators including a respective storage area configured to store data and a respective computation unit configured to perform computation, the respective storage area and the respective computation unit being configured to interact with each other;
• a controller, coupled with the one or more accelerators, the controller being configured to
• control the one or more accelerators;
• receive a command from a host;
• and
• perform an operation in response to receiving the command;
• and
• a transactional interface, coupled between the controller and the host, the transactional interface including a command and address signal channel, configured to transfer command and address signals from the host to the controller;
• the host, coupled with the transactional interface, the host being configured to send the command and address signals.

A method comprising:

• receiving, by a memory architecture, a command from a host via a transactional interface coupled between the memory architecture and the host;
• performing, by the memory architecture, an operation in response to receiving the command;
• and
• sending, by the memory architecture, a response signal indicating that the operation is completed via a response signal channel of the transactional interface to the host.