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US 2021/0173770 A1Published application
Apparatuses and methods for transferring data
AssigneeMicron Technology, Inc.
InventorsDaniel B. Penney, Gary L. Howe
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.
Claims20
An apparatus, comprising:
- a cache coupled to an array of memory cells and a data bus;
- and
- a controller coupled to the cache, the array, or the data bus, or any combination thereof, wherein the controller is to:
- perform an operation to transfer data from the array to the cache beginning at a first physical address of the cache, wherein the first physical address of the cache is neither an initial address of the cache nor a final address of the cache;
- and
- perform an operation to transfer data from the cache to the data bus concurrently with performance of the operation to transfer data from the array to the cache, wherein
- the operation to transfer the data from the cache to the data bus begins at a second physical address of the cache that is located in a physical address location that is different that the first address of the cache.
4 more elements
A method, comprising:
- transferring data from an array of memory cells to a cache beginning at a first physical address, wherein the cache comprises a plurality of physical addresses starting at an initial address and ending at a final address, and wherein the first address is neither the initial address of the cache nor the final address of the cache;
- initiating a concurrent transfer of data from the array to the cache and from the cache to a data bus coupled to the cache;
- and
- writing the data from the cache to the data bus in response to initiating the concurrent transfer of data beginning at a second address, wherein the second address is neither the initial address of the cache nor the final address of the cache.
1 more element
A system, comprising:
- an interface;
- a cache communicatively coupled to the interface;
- and
- a controller coupled to the interface and the cache, wherein the controller is configured to:
- control writing of data to the cache via the interface;
- and
- control writing the data from a first physical address of the cache to an array of memory cells while data is concurrently written from to the cache via the interface to a second physical address of the cache, wherein the first address of the cache and the second address of the cache are neither an initial address of the cache nor a final address of the cache.
4 more elements
Dependencies are inferred from the claim text.