Error-Correction-Detection Coding for Hybrid Memory Module
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
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Abstract
A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). The memory supports error-detection and correction (EDC) techniques by allocating a fraction of DRAM storage to information calculated for each unit of stored data that can be used to detect and correct errors. An interface between the DRAM cache and NVM executes a wear-leveling scheme that aggregates and distributes NVM data and EDC write operations in a manner that prolongs service life.
Claims26
A method of accessing a data page and error-detection syndromes corresponding to the data page in an erase block of a non-volatile memory (NVM) responsive to a command to a physical address, the erase block comprising an array of NVM pages, the method comprising:
- writing the data page into a first of the NVM pages at a first NVM address in the erase block of the NVM;
- and
- writing the error-detection syndromes into a second of the NVM pages at a second NVM address in the erase block of the NVM component.
Dependencies are inferred from the claim text.