Coherent access to persistent memory region range
AssigneeWestern Digital Technologies, Inc.
InventorsShay BENISTY, Ariel NAVON, Judah Gamliel HAHN
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AssigneeWestern Digital Technologies, Inc.
InventorsShay BENISTY, Ariel NAVON, Judah Gamliel HAHN
Estimating the term…
A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.
A controller, comprising:
A data storage device, comprising:
A system for storing data, comprising:
Dependencies are inferred from the claim text.