Systems and methods for defining memory sub-blocks

A controller comprising:

• a bus interface in communication with a plurality of memory blocks of a 3-dimensional memory array;
• and
• a processor configured to:
• identify a first group of bit lines corresponding to the memory blocks;
• bias the first group of bit lines to a first voltage using respective bit line biasing transistors;
• identify, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines;
• and
• logically group memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

A method for defining sub-memory blocks in a memory system, the method comprising:

• identifying a plurality of bit line groups corresponding to memory blocks of a 3-dimensional memory array;
• biasing each bit line group of the plurality of bit line groups to a respective voltage using bit line biasing transistors corresponding to each respective bit line group of the plurality of bit line groups;
• identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect with respective ones of the bit line groups of the plurality of bit line groups;
• and
• logically grouping memory addresses of memory cells for each respective sub-memory block.